Multi-port static random access memory

ABSTRACT

A multi-port static random access memory for reducing an occpation area of a layout memory cells on a substrate having the improvements from a first plurality of metal electrode layers on a first plurality of active regions included in one unit cell and in other unit cell neighbored to the corresponding one unit cell of the first plurality of metal electrode layers being commonly connected to the power supply source, comprises: a second plurality of the metal electrode layers on second plurality of the active regions and to be independently and separately connected to the power supply source, by every one unit cell in cell array.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and inparticular to a multi-port static random access memory (hereinafter,referred to as “SRAM”) having a high operation speed. Further, thepresent invention relates to SRAM in which an occupation area of memorycells laid out on a substrate can be reduced by the formation of anelectrical connection layer only within first unit cell in arrangementof memory cell array, for providing a common power supply source to thearrangement of memory cell array.

2. Description of the Related Art

In a conventional SRAM, every first unit cell has a flip-flop circuitincluding a pair of access transistors, a pair of drive transistors, anda pair of load transistors. Compared to first unit cell having aresistor as a load device in the conventional SRAM first unit cellhaving a bulk-type PMOS transistor as a load transistor has a lowerstand-by current and is good in view of memory cell stability. Moreover,it has widely been used as an embedded memory cell in a conventionalSRAM since first unit cell having a resistor as a load device and firstunit cell having a bulk-type PMOS transistor as a load transistor hadthe same steps of a production process. Therefore, a multi-port SRAM hasbeen developed for the purpose of increasing the operation speed of itsdata input/output and of having a wide system application from such aconventional SRAM. In such a multi-port SRAM, increasing the number oftransistors in first unit cell is bad in view of an integration density.Problems such as an integration density, a process margin, and areliability of an operation speed, however, now do not matter owing tothe development of a production process art. A wide system applicationcan be enough to load on people's attentions.

FIG. 1 is a circuit configuration diagram of first embodiment accordingto a conventional two-port SRAM.

In FIG. 1, a load transistor for common use, a drive transistor forcarrying out a write operation, and an access transistor forcarrying-out a read operation are shown in first unit cell. There are apair of read bit line RB and /RBB and a pair of write bit line WB and/WBB in a vertical direction. There are a power supply voltage VCC and awrite word line WWL in the upper part of first unit cell, and a powersupply ground VSS and a read word line RWL in the lower part of firstunit cell.

As be shown in FIG. 1, a pair of write access transistors WTA1 and WTA2,and a pair of read access transistors RTA1 and RTA2, a pair of loadtransistors TL1 and TL2, a pair of write drive transistors WTD1 andWTD2, and a pair of read drive transistors RTD1, and RTD2 consist offirst unit cell. All the above described transistors have a set of firstand second electrodes and gate electrode. Gate electrodes of the writeaccess transistors WTA1 and WTA2 in first unit cell are respectively andelectrically connected to a write word line WWL. Each of firstelectrodes of the write access transistors WTA1 and WTA2 is electricallycoupled to the corresponding bit line of the pair of write bit line WBand /WBB. Also, gate electrodes of the read access transistors RTA1 andRTA2 are respectively and electrically connected to the read word lineRWL. Each of first electrodes of the read access transistors RTA1 andRTA2 is electrically coupled to the corresponding read bit line of thepair of read bit lines RB and /RBB. Each of first electrodes of the loadtransistors TL1 and TL2 is respectively connected to power supplyvoltage VCC. Each of gate electrodes of the load transistors TL1 and TL2is respectively connected to a first pair of common nodes CN1 and CN2.First common node CN1 is electrically linked to second common node CN2in the first pair of common nodes CN1 and CN2. First write drivetransistor WTD1 at the pair of write drive transistors WTD1 and WTD2 andfirst read drive transistor RTD1 at the pair of read drive transistorsRTD1 and RTD2 are in series connected to first load transistor TL1 atthe pair of load transistors TL1 and TL2. Each of gate electrodes offirst write drive transistor WTD1 and first read drive transistor RTD1is respectively connected to second common node CN2 of the first pair ofthe common nodes CN1 and CN2. A serial connection of second write drivetransistor WTD2 and second read drive transistor RTD2 is linked tosecond load transistor TL2. And each of gate electrodes of second writedrive transistor WTD2 and second read drive transistor RTD2 is commonlyconnected to the first pair of common nodes CN1 and CN2. Secondelectrodes of first load transistor TL1 and first write accesstransistor WTA1 and first electrode of first write drive transistor WTD1are electrically linked to each second through first common node CN1.

Further, second electrodes of second load transistor TL2 and secondwrite access transistor WTA2 and first electrode of second write drivetransistor WTD2 are mutually connected to second common node CNB, too.Second electrode of first write drive transistor WTD1 and firstelectrode of first read drive transistor RTD1 are respectively connectedto the power supply ground VSS. Each of second electrodes of the pair ofread access transistors RTA1 and RTA2 which are PMOS transistors, isrespectively connected to the corresponding electrode of the pair ofread drive transistors RTD1 and RTD2. And write access transistors WTA1and WTA2, read access transistors RTA1 and RTA2, write drive transistorsWTD1 and WTD2, read drive transistors RTD1 and RTD2 are NMOStransistors. First electrode of first load transistor TL1 iselectrically connected to power supply voltage VCC, together with secondload transistor TL2 included in the second unit cell neighbored to thecorresponding first unit cell. Also, an electrical common connection offirst electrode of second load transistor TL2 and first load transistorincluded in second unit cell neighbored to the corresponding first unitcell is made via power supply voltage VCC. First write drive transistorWTD1 and first read drive transistor RTD1 transistor included in firstunit cell are electrically linked to power supply ground VSS, togetherwith second write drive transistor and second read drive transistorneighbored to the corresponding first unit cell. Second write drivetransistor WTD2 and second read drive transistor RTD2 are electricallycoupled to power supply ground VSS, together with write drive transistorand read drive transistor included in second unit cell neighbored to thecorresponding first unit cell.

FIG. 2 a to FIG. 2 i are patterned layout configuration diagrams forexplaining process steps of first embodiment of a two-port SRAMaccording to a prior art invention.

In FIG. 2 a, an N-type well region 22 is formed on first part of a cellformation region 21 in order to define a PMOS transistor which is usedas a load transistor, wherein the cell formation region 21 is not afixed region, rather than can be varied. Second region except the N-typewell region 22 in the cell formation region 21 is a P type well region.By a formation of a device isolation layer (not shown) in a field region23 of the cell formation region 21 are made first to seventh activeregions 24 a to 24 g as shown in FIG. 2 b. In FIG. 2 c, first to fourthelectrode patterned layers 25 a to 25 d are passed through over at leastany first portion of the first to seventh active regions 24 a to 24 g.By exposing the first to seventh active regions 24 a to 24 g using thefirst to fourth electrode patterned layers 25 a to 25 d impurity regions(not shown) are formed within the substrate surfaces of their regions 24a to 24 g. A selective exposure of the impurity regions or the first toseventh active regions 24 a to 24 g makes a formation of a plurality ofcontact regions 26 which are selectively etched after repeatedlycarrying out a formation of an insulation layer between first layer anda corresponding second layer over contact regions 26 in FIG. 2 d.

As shown in FIG. 3 a, an N-type well region 22 is formed in order tofunction as a pair of first and second load transistors TL1 and TL2. Aformation of first and second active regions 24 a and 24 b is made by aseparation of the N-type well region 22 to horizontal direction. In someregion except N type well region 22 in the cell formation region 21which is a P-type well region, third and fourth active regions 24 c and24 d which face each second are formed by meeting at least firstextension portion to a perpendicular direction from an intersectionbetween a long axis of a horizontal direction and a long axis of avertical direction. Also, fifth active region 24 e is formed on aseparation region of first and second active regions 24 a and 24 b.Sixth and seventh active regions 24 f and 24 g are respectively formedon left and right lower portions of third and fourth active regions 24 cand 24 d. A first metal electrode layer 25 a is formed in order to beutilized as gate electrodes of first load transistor TL1, first writedrive transistor WTD1, and first read drive transistor RTD1. First metalelectrode layer 25 a has a configuration in which a central portion offirst active region 24 a is passed on in a vertical direction and atleast two portions of third active regions 24 c are passed on. Secondmetal electrode layer 25 a is formed so that a central portion of secondactive regions 24 d are passed on. As gate electrodes of second loadtransistor TL2, second write drive transistor WTD2, and second readdrive transistor RTD2 functions first metal electrode layer 25 a. Thirdmetal electrode layer 25 c is formed in order to be utilized as gateelectrodes of first and second write access transistors WTA1 and WTA2.Third metal electrode layer 25 c has a configuration in which third andfourth active regions 24 c and 24 d are respectively passed on tovertical direction and their vertical extension portions are met at apredetermined position with each second so that a horizontal extensionportion is formed in a horizontal direction. Fourth metal electrodelayer 25 d which is utilized as gate electrodes of first and second readaccess transistor RTA1 and RTA2, is formed so that the lower portions ofthird and fourth active regions 24 c and 24 d are passed on at the sametime. Further, a plurality of contact regions 26 are formed on first toseventh active regions 24 a to 24 g of which any portion are not passedon by first to fourth first to fourth metal electrode layer 25 a to 25 dor on first to fourth metal electrode layer 25 a to 25 d. Fifth activeregion 24 e is formed in order to be defined as well bias of N type wellregion 22. After carrying out a process step for the purpose ofobtaining the above described patterned configuration, a process stepfor forming a first group of metal electrical wires including metalelectrical wire layers 27 a to 27 m is performed as shown in FIG. 2 e.

In FIG. 2 e, first to fifth metal electrical wire layers 27 a to 27 eare formed in order to be utilized as a power supply voltage VCC, awrite word line WWL, a read word line RWL, etc., and sixth to thirteenthmetal electrical wire layers 27 f to 27 e are formed in order to beutilized as an interior electrical wire. A plurality of via holes 28 areformed, as shown in FIG. 2 f, on first to thirteenth metal electricalwire layers 27 a to 27 e. In FIG. 3 b, first metal electrical wire layer27 a is electrically contacted with first electrodes of first and secondload transistors TL1 and TL2. A electrical connection of gate electrodesof first load transistor TL1, first write drive transistor WTD1, andread drive transistor RTD1, and first common node CN1 is made by secondmetal electrical wire layer 27 b. Third metal electrical wire layer 27 ccauses second common node CN2 to make an electrical connection of gateelectrodes of second load transistor TL2, second write drive transistorWTD2, and second read drive transistor RTD2. Fourth metal electricalwire layer 27 d which is a horizontal extension, is formed in order toelectrically contact with gate electrodes of first and second writeaccess transistor WTA1 and WTA2. In order to electrically contact withgate electrodes of first and second read access transistors RTA1 andRTA2, fifth metal electrical wire layer 27 e is formed. Sixth andseventh metal electrical wire layer 27 f and 27 g are formed in order toelectrically contact with first electrodes of first and second writeaccess transistors WTA1 and WTA2. Eighth and ninth metal electrical wirelayers 27 h and 27 i are formed in order to be electrically contactedwith first electrodes of first and second read access transistors RTA1and RTA2. With third common node CN3 of first write drive transistorWTD1 and first read drive transistor RTD1 is electrically contactedtenth metal electrical wire layer 27 j. Eleventh metal electrical wirelayer 27 k is formed in order to electrically contact with fourth commonnode CN4 of second write drive transistor WTD2 and second read drivetransistor RTD2. Twelfth and thirteenth metal electrical wire layers 27l and 27 m are formed in order to contact with power supply voltage VCC.First plurality of via holes are respectively formed on sixth tothirteenth metal electrical wire layer 27 f to 27 m. After carrying outprocess step for the purpose of obtaining the patterned configuration asshown in FIG. 2 e, process step for forming a second group of metalelectrical wires including metal electrical wire layers 29 a to 29 f isperformed as shown in FIG. 2 g.

In FIG. 2 g, first metal electrical wire layer 29 a and second metalelectrical wire layer 29 b are formed so that these metal electricalwire layers 29 a and 29 b may pass on edge parts of both left and rightportions of a cell formation region 21 to a vertical direction. Firstmetal electrical wire layer 29 a and second metal electrical wire layer29 b function as power supply ground VSS. Third and fourth metalelectrical wire layers 29 c and 29 d are formed in order to function asa pair of read bit line RB and /RBB. Also, third and fourth metalelectrical wire layers 29 e and 29 f are separated from each second at apredetermined distance between first and second metal electrical wirelayers 29 a and 29 b so that these metal electrical wire layers 29 c and29 d may face. Fifth and sixth metal electrical wire layers 29 e and 29f are formed, for the purpose of functioning as a pair of write bitlines WB and /WBB, so that third and fourth metal electrical wire layers29 c and 29 d are separated from each second at a predetermined distancebetween third and fourth metal electrical wire layers 29 c and 29 d witha shape of an inverse face of these metal electrical wire layers 29 eand 29 f On any end of first and second metal electrical wire layers aresecond plurality of via holes 30, for the purpose of contacting withpower supply ground VSS as known in FIG. 2 f. Further, a third group ofmetal electrical wires including metal electrical wire layers 31 a to 31c are formed in a horizontal direction as known in FIG. 2 g.

In FIG. 3 c, tenth electrical wire layer 27 j and twelfth electricalwire layer 27 l of the first metal electrical wire group areelectrically coupled through first via holes to first electrical wirelayer 29 a of the second metal electrical wire group. Eleventhelectrical wire layer 27 k and thirteenth electrical wire layer 27 m ofthe first metal electrical wire group are electrically contacted throughfirst via holes with second electrical wire layer 29 b of the secondmetal electrical wire group. Eighth electrical wire layer 27 h of thefirst metal electrical wire group are electrically contacted throughfirst via holes with third electrical wire layer 29 c of the secondmetal electrical wire group. Ninth electrical wire layer 27 i of thefirst metal electrical wire group are electrically contacted throughfirst via holes with fourth electrical wire layer 29 d of the secondmetal electrical wire group. Sixth electrical wire layer 27 f of thefirst metal electrical wire group are electrically contacted throughfirst via holes with fifth electrical wire layer 29 e of the secondmetal electrical wire group. Seventh metal electrical wire layer 27 g ofthe first metal electrical wire group are electrically contacted throughfirst via holes with sixth electrical wire layer 29 f of the secondmetal electrical wire group. All first to sixth metal electrical wirelayers 29 a to 29 f have a vertical extension.

First and second electrical wire layers 29 a and 29 b of the secondmetal electrical wire group are electrically contacted through first viaholes with first electrical wire layer 31 a of the third metalelectrical wire group. First metal electrical wire layer 31 a has ahorizontal extension. As a write global word line GWL_W second metalelectrical wire layer 31 b of the third metal electrical wire group isutilized. Third metal electrical wire layer 31 c of the third metalelectrical wire group is utilized as a read global word line GWL_R.Second metal electrical wire layer 31 b and third metal electrical wirelayer 31 c of the third metal electrical wire group are separated fromeach second at a predetermined horizontal distance. Configurations shownin FIG. 3 a to FIG. 3 c are an original patterned configuration in whichall layers between first layer and second successive layer areoverlapped. However, it is difficult to be distinct from a boundary ofvarious regions in case of the show of the overlapped configurationwithin FIG. 3 a to FIG. 3 c. Therefore, the overlapped configuration isnot shown in FIG. 3 a to FIG. 3 c.

FIG. 4 a to FIG. 4 c are patterned layout configuration diagrams forexplaining process steps of other embodiment of a two-port SRAMaccording to a prior art invention. In other embodiment of the prior arttwo-port SRAM, a long axis of active regions for forming first andsecond load transistors TL1 and TL2 is a vertical direction.

In FIG. 4 a, an N type well region 42 is formed on first part of a cellformation region 41 in order to define first and second load transistorsTL1 and TL2. First and second active regions 44 a and 44 b is formed sothat these active regions 44 a and 44 b are separated from each secondwithin cell formation region 41. A vertical direction of these activeregions 44 a and 44 b is a long axis. In second region except the N-typewell region 42 in the cell formation region 41 which is a P-type wellregion, third and fourth active regions 44 c and 44 d which face eachsecond are formed by meeting at least first extension portion to aperpendicular direction from an intersection between a long axis of ahorizontal direction and a long axis of a vertical direction. Also,fifth active region 44 e is formed on a separation region of first andsecond active regions 44 a and 44 b.

Sixth and seventh active regions 44 f and 44 g are respectively formedon left and right lower portions of third and fourth active regions 44 cand 44 d. A first metal electrode layer 45 a is formed in order to beutilized as gate electrodes of first load transistor TL1, first writedrive transistor /WTD1, and first read drive transistor RTD1. Firstmetal electrode layer 45 a has a configuration in which a centralportion of first active region 44 a is passed on in a vertical directionand at least two portions of third active regions 44 c are passed on.Second metal electrode layer 45 b is formed so that a central portion ofsecond active region 44 b is passed on in a horizontal direction and atleast two portions of fourth active regions 44 d are passed on. As gateelectrodes of second load transistor TL2, second write drive transistorWTD2, and second read drive transistor RTD2 functions second metalelectrode layer 45 b. Third metal electrode layer 45 c is formed inorder to be utilized as gate electrodes of first and second write accesstransistors WTA1 and WTA2. Fifth metal electrode layer 45 d is formed inorder to be utilized as gate electrodes of first and second read accesstransistors RTA1 and RTA2. A plurality of contact regions 46 are formedon first to seventh active regions 44 a to 44 g of which any portion arenot passed on by first to fourth metal electrode layers 45 a to 45 d oron first to fourth metal electrode layers 45 a to 45 d. Fifth activeregions 44 e is formed in order to define a bias of the N-type wellregion 42.

In FIG. 4 b, first metal electrical wire layer 47 a is electricallycontacted with first electrodes of first and second load transistor TL1and TL2. A electrical connection of gate electrodes of first loadtransistor TL1, first write drive transistor WTD1, and read drivetransistor RTD1 and first common node CN1 are made by second metalelectrical wire layer 47 b. Third metal electrical wire layer 47 ccauses second common node CN2 to make an electrical connection of gateelectrodes of second load transistor TL2, second write drive transistorWTD2, and second read drive transistor RTD2. Fourth metal electricalwire layer 47 d which is a horizontal extension, is formed in order toelectrically contact with gate electrodes of first and second writeaccess transistor WTA1 and WTA2. In order to electrically contact withgate electrodes of first and second read access transistors RTA1 andRTA2, fifth metal electrical wire layer 47 e is formed. Sixth andseventh metal electrical wire layer 47 f and 47 g are formed in order toelectrically contact with first electrodes of first and second writeaccess transistors WTA1 and WTA2. Eighth and ninth metal electrical wirelayers 47 h and 47 i are formed in order to electrically contact withfirst electrodes of first and second read access transistors RTA1 andRTA2. With third common node CN3 of first write drive transistor WTD1and first read drive transistor RTD1 is electrically contacted tenthmetal electrical wire layer 47 j. Eleventh metal electrical wire layer47 k is formed in order to electrically contact with fourth common nodeCN4 of second write drive transistor WTD2 and second read drivetransistor RTD2. Twelfth and thirteenth metal electrical wire layers 47l and 47 m are formed in order to contact with power supply ground VSS.First plurality of via holes are respectively formed on sixth tothirteenth metal electrical wire layers 47 f to 47 m. First metalelectrical wire layer of first metal electrical wire group has a firstand second active regions 44 a and 44 b of which a long axis is extendedto a vertical direction. Source and drain electrodes are positioned atthe same layer as fifth active region 44 e, thereby having a straightand vertical extension.

In FIG. 4 c, first metal electrical wire layer 49 a of second metalelectrical wire group is formed so that its electrical wire layers 49 ais contacted through first via holes with tenth and twelfth metalelectrical wire layers 47 j and 47 l of first metal electrical wiregroup to a vertical direction. Second metal electrical wire layer 49 bof second metal electrical wire group is formed so that its electricalwire layers 49 b is contacted through first via holes with eleventh andthirteenth metal electrical wire layers 47 k and 47 m of first metalelectrical wire group to a vertical direction. Third metal electricalwire layer 49 c of second metal electrical wire group is formed so thatits electrical wire layers 49 c is contacted through first via holeswith eighth metal electrical wire layer 47 h of first metal electricalwire group to a vertical direction. Fourth metal electrical wire layer49 d of second metal electrical wire group is formed so that itselectrical wire layers 49 d is contacted through first via holes withninth metal electrical wire layer 47 i of first metal electrical wiregroup to a vertical direction. Fifth metal electrical wire layer 49 e ofsecond metal electrical wire group is formed so that its electrical wirelayers 49 e is contacted through first via holes with sixth metalelectrical wire layer 47 f of first metal electrical wire group to avertical direction. Sixth metal electrical wire layer 49 f of secondmetal electrical wire group is formed so that its electrical wire layers49 f is contacted through first via holes with seventh metal electricalwire layer 47 g of first metal electrical wire group to a verticaldirection. First metal electrical wire layer 51 a of third metalelectrical wire group is formed so that its electrical wire layers 51 ais contacted through second via holes with first and second metalelectrical wire layers 49 a and 49 b of second metal electrical wiregroup to a horizontal direction. As a write global word line GWL_Wsecond metal electrical wire layer 51 b of the third metal electricalwire group is utilized. Third metal electrical wire layer 51 c of thethird metal electrical wire group is utilized as a read global word lineGWL_R.

In the above-described SRAM, each electrode at the load transistorsincluded in first unit cell and in second unit cell neighbored to thecorresponding first unit cell is mutually connected to power supplysource line, thereby being happened at the same time at in-operation ofall unit cells that are linked to power supply line VCCL. Also, commonelectrodes of write drive transistor and read drive transistor in everyunit cell are electrically connected to power supply ground VSS, suchthat a problem is happened at the same time at all unit cells that arelinked to power supply ground VSS.

Further, the conventional SRAM cell had the second problem thatoccupation region of a load transistor for obtaining a loading effect isnarrow in its width because the width of the load transistor is extendedto a vertical direction, resulting in degrading its trust and decreasingits operation speed.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide amulti-port SRAM which can reduce an occupation area of first unit cellon a substrate.

Other object of the present invention is to provide a multi-port SRAMwhich increase an operation speed.

To achieve the above objects, a multi-port SRAM according to the presentinvention in 2-port static random access memory comprising a firstplurality of active regions which are separated from each second withina cell formation region, a first plurality of metal electrode layerswhich are respectively passed on the first plurality of active regions,and a power supply source which is electrically contacted with firstplurality of the metal electrode layers, wherein the metal electrodelayers included in first unit cell and in second unit cell neighbored tothe corresponding first unit cell of the first plurality of metalelectrode layers are commonly connected to the power supply source,having the improvements comprise: a second plurality of active regionsformed within the cell formation region, and a second plurality of metalelectrode layers to be passed on second plurality of the active regionsand to be independently and separately connected to the power supplysource, wherein the independence and separation of the connection to thepower supply source is between the metal electrode layers included infirst unit cell in second plurality of the metal electrode layers andthe metal electrode layers included in the second unit cell neighboredto the corresponding first unit cell in second plurality of the metalelectrode layers. The upper portion of second plurality of the activeregions are respectively and commonly contacted with a write word lineand the lower portion of second plurality of the active regions arerespectively and commonly contacted with a read word line, only in thefirst unit cell regardless of second unit cell neighbored to thecorresponding first unit cell.

Further, a multi-port SRAM according to the present invention having aplurality of unit cells each includes: a first pair of first and secondload transistors having their gate electrode electrodes respectivelyformed by first and second metal electrode layers on first and secondactive regions, their first electrodes for being electrically contactedwith a power supply voltage, and their second electrodes for beingelectrically connected to a first pair of first and second common nodesonly in first unit cell, regardless of second unit cell neighbored tothe corresponding first unit cell; a first pair of first and secondwrite drive transistors having their gate electrodes and firstelectrodes for being electrically and respectively connected to thecorresponding first of first pair of first and second common nodes; afirst pair of first and second read drive transistors having their firstelectrodes for being electrically and respectively connected to thecorresponding first of a second pair of third and fourth common nodes,and their gate electrodes for being electrically and respectivelyconnected to the corresponding first of first pair of first and secondcommon nodes; a first pair of first and second write access transistorshaving their first electrodes for being electrically and respectivelyconnected to the corresponding first of first pair of common nodes,their gate electrodes for being electrically and respectively connectedto the corresponding first of second electrodes of the pair of first andsecond load transistors, and their second electrodes for beingelectrically and respectively connected to the corresponding first of apair of write bit lines; a first pair of first and second read accesstransistors having their gate electrodes for being electrically andrespectively connected to the corresponding first of a pair of read wordlines, their first electrodes for being electrically and respectivelyconnected to the corresponding first of the pair of first and secondread drive transistors, and their second electrodes for beingelectrically and respectively connected to the corresponding first of apair of read bit lines; a plurality of active regions formed within thecell formation region; a plurality of metal electrode layers to bepassed on the active regions and to be independently and separatelyconnected to the power supply source; a plurality of metal electricalwire groups having: first metal electrical wire group consisting offirst metal electrical wire layer for being electrically contacted withthe contact regions of said power supply voltage and with firstelectrodes of first and second load transistors; second and third metalelectrical wire layers for being respectively coupled to thecorresponding contact region of the write word lines; fourth metalelectrical wire layer for being electrically connected to first to thirdcontact regions for first common node; sixth and seventh metalelectrical wire layers for being electrically connected to the contactregions of the pair of write bit lines; eighth and ninth metalelectrical wire layers for being electrically connected to thecorresponding contact region of the read word lines; tenth metalelectrical wire layer for being electrically connected to the contactregions of the power supply ground and is extended to the upper side ofthird active region; and eleventh and twelfth metal electrical wirelayers for being electrically connected to the contact regions of thepair of the read bit lines, a second metal electrical wire groupconsisting of first metal electrical wire layer for being electricallycontacted with first metal electrical wire layer of first metalelectrical wire group and for being utilized as said power supplyvoltage; second metal electrical wire layer for being electricallycontacted with second and third metal electrical wire layers of firstmetal electrical wire group; third to fifth metal electrical wire layersfor being electrically contacted with second and third metal electricalwire layers of first metal electrical wire group; third to fifth metalelectrical wire layers for being electrically contacted with sixth,seventh, and tenth metal electrical wire layers of first metalelectrical wire group; sixth metal electrical wire layer for beingelectrically contacted with eighth and ninth metal electrical wirelayers of first metal electrical wire group and for functioning as thecorresponding first of the read word lines; and seventh and eighth metalelectrical wire layers for being separated from each second and forbeing electrically contacted with eleventh and twelfth metal electricalwire layers of first metal electrical wire group, and a third metalelectrical wire group consisting of first and second metal electricalwire layers for being utilized as the pair of the write bit lines andfor being electrically contacted with third and fourth metal electricalwire layers of second metal electrical wire group via a second pluralityof via holes; third and fourth metal electrical wire layers for beingutilized as the pair of read bit lines and for being electricallycontacted with seventh and eighth metal electrical wire layers of secondmetal electrical wire group; fifth metal electrical wire layers forfunctioning as the power supply ground and for being electricallycontacted with fifth metal electrical wire layer of second metalelectrical wire group.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects, features and advantages of the present invention willbecome more apparent from the following detailed description when takenin conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit configuration diagram of one embodiment according toa conventional two-port SRAM.

FIG. 2 a to FIG. 2 i are patterned layout configuration diagrams forexplaining process steps of one embodiment of a two-port SRAM accordingto a prior art invention.

FIG. 3 a to 3 c are patterned layout configuration diagrams forexplaining process steps of one embodiment of a two-port SRAM accordingto a prior art invention, after forming a metal electrical wire.

FIG. 4 a to FIG. 4 c are patterned layout configuration diagrams forexplaining process steps of second embodiment of a two-port SRAMaccording to a prior art invention.

FIG. 5 is a circuit diagram for explaining process steps of firstembodiment of a multi-port SRAM according to the present invention.

FIG. 6 a to FIG. 6 i are layout schematic diagrams for explainingprocess steps of first embodiment of a multi-port SRAM according to thepresent invention.

FIG. 7 a to FIG. 7 c are layout schematic diagrams for explainingprocess steps of first embodiment of a multi-port SRAM according to thepresent invention after forming a metal electrical wire.

FIG. 8 a to FIG. 8 c are layout schematic diagrams for explainingprocess steps of second embodiment of a multi-port SRAM according to thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Best preferred embodiments of the present invention will now bedescribed with reference to the accompanying drawings. In theaccompanying drawings, the same parts as those of the prior art SRAMdenote the same symbols as those of the prior art SRAM.

FIG. 5 is a circuit configuration diagram of one embodiment of amulti-port SRAM according to the present invention.

In FIG. 5, symbol RB denotes a read bit line, symbol /RBB an invertedread bit line, symbol WB a write bit line, symbol /WBB an inverted writebit line, symbol WWL a write word line, symbol RWL a read word line,symbol WTA a write access transistor, symbol RTA a read accesstransistor, symbol CN a common node, symbol TL load transistor, symbolWTD a write drive transistor, symbol RTD a read drive transistor, symbolVCC a power supply voltage and symbol VSS denotes a power supply ground.

In FIG. 5, a read bit line RB, an inverted read bit line /RBB, a writebit line WB, and an inverted write bit line /WBB included in first unitcell are arranged in a vertical direction. And in the upper part offirst unit cell, a power supply voltage VCC and a write word line WWLare arranged in a horizontal direction. In the lower part of first unitcell, power supply ground VSS and a read word line RWL are arranged in ahorizontal direction.

Gate electrodes of write access transistors WTA1 and WTA2 included insecond unit cell neighbored to the corresponding first unit cell areelectrically connected to a write word line WWL, and first electrodes ofwrite access transistors WTA1 and WTA2 are electrically connected to apair of write bit lines WB and /WBB. Gate electrodes of read accesstransistors RTA1 and RTA2 are commonly connected to a read word lineRWL, and first electrodes of read access transistors RTA1 and RTA2 areconnected to a pair of read bit lines RB and /RBB.

Gate electrodes of first and second load transistors TL1 and TL2 areelectrically connected to a first pair of common nodes CN1 and CN2, andfirst electrodes of first and second load transistors TL1 and TL2 areelectrically connected to a power supply voltage VCC, independently fromsecond unit cell neighbored to the corresponding first unit cell. Gateelectrodes of first write access transistor WTD1 and first read accesstransistor RTD1 are electrically connected to second common node CN2 andin series to first load transistor TL1. Gate electrodes of second writeaccess transistor WTD2 and second read access transistor RTD2 areelectrically connected to first common node CN1 and in series to secondload transistor TL2.

In FIG. 5, second electrodes of first load transistor TL1 and firstwrite access transistor WTA1, and first electrode of first write drivetransistor WTD1 are electrically connected to first common node CN1. Andsecond electrodes of second load transistor TL2 and second write accesstransistor WTA2, and first electrode of second write drive transistorWTD2 are electrically connected to second common node CN2. Also, secondelectrodes of first and second write drive transistors WTD1 and WTD2 andfirst electrodes of first and second read drive transistors RTD1 andRTD2 are electrically connected to a power supply ground VSS,independently from second unit cell neighbored to the correspondingfirst unit cell. Further, the second electrodes of first and second readaccess transistors RTA1 and RTA2 are mutually connected to the secondelectrodes of first and second read drive transistors RTD1 and RTD2.Wherein first and second load transistors TL1 and TL2 are PMOStransistors, and first second write access transistors WTA1 and WTA2,first and second read access transistors RTA1 and RTA2, first and secondwrite drive transistors WTD1 and WTD2, and first and second read drivetransistors RTD1 and RTD2 are respectively a NMOS transistor.

Read and write operations of a multi-port SRAM according to the presentinvention will be in detail described now.

Supposing that a level of data stored in a unit cell is high, level ofan electrical signal at first common node CN1 is high, and therefore astate of second load transistor TL2 is a turn-off. At this time, statesof second write drive transistor WTD2 and second read drive transistorRTD2 are respectively a turn-on. Also, level of an electrical signal atfirst common node CN2 is low and therefore a state of first loadtransistor TL1 is a turn-on and states of first write drive transistorWTD1 and first read drive transistor RTD1 are respectively a turn-off.

At this situation, when a level of an electrical signal “high” iswritten into a unit cell a level of an electrical signal at a write wordline WWL is high and a level of an electrical signal at a read word lineRWL is low, and therefore first and second write access transistors WTA1and WTA2 are turned on and first and second read access transistors RTA1and RTA2 are turned off. Successively, a level of an electrical signalat a write bit line WB is low and a level of an electrical signal at aninverted write bit line /WBB is high. At this time, a level of anelectrical signal at first common node CN1 is low via first write accesstransistor WTA1 because a current driving function of first loadtransistor TL1 is worse than that of first write access transistor WTA1,and therefore second load transistor TL2 is turned on and second readdrive transistor RTD2 is turned off. Resultantly, a level of anelectrical signal at second common node CN2 is high, first loadtransistor TL1 is turned off, and first write drive transistor WTD1 andfirst read drive transistor RTD1 are continue to be turned on. And levelof data to be stored in a unit cell is “0”. A completion of a writeoperations of a multi-port SRAM according to the present invention ismade. In case of a read operations of a multi-port SRAM according to thepresent invention, if a unit cell is selected in order to read-out astored data “0” from a selected unit cell of a cell array a level of aread word line RWL is high and a level of a write word line WWL is low.Therefore, first and second read access transistors RTA1 and RTA2 areturned on and first and second write access transistors WTA1 and WTA2are turned off A level of an electrical signal at first common node CN1is low and a level of an electrical signal at second common node CN2 ishigh because a level of data stored in a cell is “0”. Also, second loadtransistor TL2 is turned on and second write drive transistor WTD2 andsecond read drive transistor RTD2 are continue to be turned off. Andfirst write drive transistor WTD1 and first read drive transistor RTD1are continue to be turned on. Trough first read access transistor RTA1and first read drive transistor RTD1 a read bit line RB is low. By theturned-off state of second read drive transistor RTD2, a level of aninverted read bit line /RBB is high. The stored data “0” from theselected unit cell of a cell array is red-out by sensing a difference ofvoltages on a pair of read bit lines RB and /RBB.

FIG. 6 a to FIG. 6 i are schematic layout diagrams for explainingprocess steps of one embodiment of a multi-port SRAM according to thepresent invention.

In FIG. 6 a, an N-type well region 62 is formed within first region of acell formation region 61 in order to function as a pair of first andsecond load transistors TL1 and TL2. Some region except the N-type wellregion 62 within the cell formation region 61 indicate a P-type wellregion.

As known from FIG. 6 b, a formation of first to thirteen active regions64 a to 64 m is made by a separation of second region (not shown) from afield region 63 in the cell formation region 61. Of first to thirteenactive regions 64 a to 64 m, first, second and fourth active regions 64a, 64 b, and 64 d are independently separated from each second andsecond regions except the above active regions 64 c, 64 e, 64 f, 64 g,64 h, 64 i, 64 j, 64 k, 64 l, and 64 m are dependently integrated fromeach second. First metal electrode layer 65 a has a configuration inwhich its two portions are perpendicular to each second and at leastfirst portion of first, third, and sixth active regions 64 a, 64 c, and64 f are passed on. Second metal electrode layer 65 b is formed so thatit may have a symmetrically mutual face configuration with first metalelectrode layer 65 a and at least first portion of second, third,seventh active regions 64 b, 64 c, and 64 g may be passed on. Thirdmetal electrode layer 65 c is formed so that any portion of third activeregion 64 c is passed on. Fourth metal electrode layer 65 d is formed sothat any portion of third active region 64 c may be passed on. Fifthmetal electrode layer 65 e is formed so that any portion of tenth activeregion 64 j may be passed on. Sixth metal electrode layer 65 f is formedso that it may have a symmetrically mutual face configuration with fifthmetal electrode layer 65 e and at least any portion of eleventh activeregions 64 k may be passed on.

Using the metal electrode layers, the impurities regions (not shown) areformed within the surface of exposed active regions.

In FIG. 6 d, for the purpose of selectively exposing the impuritiesregions or the metal electrode layers, a plurality of contact regions 66are formed. Over the plurality of contact regions 66 is formed aninterleave layer insulation whish is selectively etched.

At this situation on the completion of formation of the contact regions,entire layout configuration will be described below.

As shown in FIG. 7 a, an N-type well region 62 is formed within some ofa cell formation region 61 in order to function as a pair of first andsecond load transistors TL1 and TL2. First and second active regions 64a and 64 b have their long axes which are perpendicular to a verticaldirection in the cell formation region 61 and are separated from eachsecond at an opposition. On the central portion of P type well regionwhich is second region except the N type well region 62 within the cellformation region 61 are third active region 64 c which has its long axisin a horizontal direction. Also, fourth active region 64 d is aseparation region between first and second active regions 64 a and 64 b.Fifth active region 64 e is formed to be extended from the central lowerportion of third active region 64 c to a vertical direction. At thelower portion of fifth active region 64 e, sixth and eighth activeregions 64 f and 64 h are respectively extended to its left side in ahorizontal direction and seventh and ninth active regions 64 g and 64 iare respectively extended to its right side in a horizontal direction.Tenth and twelfth active regions 64 j and 64 l and eleventh and thirteenactive regions 64 m and 64 k have a symmetrically face configuration atan opposition. These active regions 64 j and 64 l are respectivelyextended to their lower portions to be vertical against eighth activeregion 64 h. These active regions 64 m and 64 k are respectivelyextended to their lower portions to be vertical against seventh activeregion 64 g. As gate electrodes of first load transistor TL1, firstwrite drive transistor WTD1, and first read drive transistor RTD1 isutilized first metal electrode layer 65 a which includes a first part topass on the central of first active region 64 a in a horizontaldirection and a second part to pass on the first part in verticaldirection. Second metal electrode layer 65 b has a face configurationagainst first metal electrode layer 65 a. As gate electrodes of secondload transistor TL2, second write drive transistor WTD2, and second readdrive transistor RTD2 is utilized second metal electrode layer 65 bwhich passes on the central of second active region 64 b in a horizontaldirection and cross-passes on third and sixth active regions 64 c and 64f in vertical direction. Third and fourth metal electrode layers 65 cand 65 d are utilized as gate electrodes of first and second writeaccess transistors WTA1 and WTA2 which cross-passes third active accesstransistor 64 c through their both sides on basis of first and secondmetal electrode layers 65 a and 65 b. Fifth and sixth metal electrodelayers 65 e and 65 f are utilized as gate electrode electrodes of firstand second access transistors RTA1 and RTA2 which have a configurationin which tenth and eleventh active regions 64 j and 64 k arecross-passed in a horizontal direction. First to third contact regionsCT11, CT12, and CT13 for first common node CN1 are respectively formedon third active region 64 c of first electrodes of third metal electrodelayer 65 c, the upper portion of second metal electrode layer 65 b,first active region 64 a of second electrode of first metal electrodelayer 65 a, and the contact region of a power supply voltage VCC formedon first and second active regions 64 a and 64 b and fourth activeregion 64 d of first and second metal electrode layers 65 a and 65 b.First to third contact regions CT21, CT22, and CT23 for second commonnode CN2 are respectively formed on third active region 64 c of firstelectrodes of fourth metal electrode layers 65 d, the upper portion offirst metal electrode layer 65 a, and second active region 64 b ofsecond electrode of second metal electrode layer 65 b. Contact regionsof a pair of write bit lines WB and /WBB are respectively formed onthird active region 64 c of second electrodes of third and fourth metalelectrode layers 65 c and 65 d.

Contact regions of a write word line WLL are respectively positioned atthe edge of the cell formation region 61 and are respectively formed onthe end portion of third and fourth metal electrode layers 65 c and 65d. Contact regions of a power supply ground VSS are formed on fifthactive region 64 e. Contact regions of a read word line RWL arerespectively positioned at the edge of the cell formation region 61 andare respectively formed on the end portion of fifth and sixth metalelectrode layers 65 e and 65 f Contact regions of a pair of read bitlines RB and /RBB are respectively formed on twelfth and thirteen activeregions 64 l and 64 m of first electrodes of fifth and sixth metalelectrode layers 65 e and 65 f Fourth active region 64 d is a region formediating a well bias of the N-type well region. On the completion ofthe process step of the above described layout configuration as shown inFIG. 7 a, first metal electrical wire layer 67 a of first metalelectrical wire group for functioning as a power supply voltage VCC andsecond to twelfth metal electrical wire layers 67 b to 67 l of firstmetal electrical wire group are formed as shown in FIG. 6 e.

In FIG. 6 f, a plurality of via holes are formed on the active regionsand the metal electrical wire layers of first metal electrical wiregroup.

In FIG. 7 b, first metal electrical wire layer 67 a of first metalelectrical wire group is electrically contacted with contact regions ofa power supply voltage VCC of fourth active region 64 d and firstelectrodes of first and second load transistors TL1 and TL2. Second andthird metal electrical wire layer 67 b and 67 c of first metalelectrical wire group are respectively coupled to a contact region of awrite word line WWL. Fourth metal electrical wire layer 67 d of firstmetal electrical wire group is electrically connected to first to thirdcontact regions CT11, CT12, and CT13 for first common node CN1. Sixthand seventh metal electrical wire layers 67 f and 67 g of first metalelectrical wire group are electrically connected to contact regions of apair of write bit lines WB and /WBB. Eighth and ninth metal electricalwire layers 67 h and 67 j of first metal electrical wire group areelectrically connected to contact region of a read word line RWL. Tenthmetal electrical wire layer 67 j of first metal electrical wire group iselectrically connected to contact regions of a power supply ground VSSand is extended to the upper side of third active region 64 c. Eleventhand twelfth metal electrical wire layers 67 k and 67 l of first metalelectrical wire group are electrically connected to contact regions of apair of read bit lines RB and /RBB. A first plurality of via holes 68are formed on first to twelfth metal electrical wire layers 67 a to 67 lof first metal electrical wire group. After carrying out the processstep of the above described layout configuration as shown in FIG. 7 a,first to eighth metal electrical wire layers 69 a to 69 h of secondmetal electrical wire group for functioning as a power supply voltageVCC, a write word line WWL, and a read word line RWL are formed as shownin FIG. 6 g. A second plurality of via holes 70 are formed on third toeighth metal electrical wire layers 69 c to 69 h. Successively, first tosixth metal electrical wire layers 71 a to 71 e are formed in a verticaldirection as shown in FIG. 6 i.

In FIG. 7 c, first metal electrical wire layer 69 a of second metalelectrical wire group is electrically contacted with first metalelectrical wire layer 67 a of first metal electrical wire group and isutilized as a power supply voltage VCC. Second metal electrical wirelayer 69 b of second metal electrical wire group is electricallycontacted with second and third metal electrical wire layers 67 b and 67c of first metal electrical wire group. Third to fifth metal electricalwire layer 69 c to 69 e of second metal electrical wire group areelectrically contacted with sixth, seventh, and tenth metal electricalwire layers 67 f, 67 g, and 67 j of first metal electrical wire group.Sixth metal electrical wire layer 69 f of second metal electrical wiregroup is electrically contacted with eighth and ninth metal electricalwire layers 67 h and 67 i of first metal electrical wire group forfunctioning as a read word line RWL. Seventh and eighth 69 g and 69 hare separated from each second and are electrically contacted witheleventh and twelfth. A second plurality of via holes 70 are formed onthird, fourth, fifth, seventh, and eighth metal electrical wire layers69 c, 69 d, 69 e, 69 g, and 69 h.

First and second metal electrical wire layers 71 a and 71 b of thirdmetal electrical wire group for being utilized as a pair of write bitlines WB and /WBB are electrically contacted with third and fourth metalelectrical wire layers 69 c and 69 d of second metal electrical wiregroup via the second plurality of via holes. Third and fourth metalelectrical wire layers 71 c and 71 d of third metal electrical wiregroup for being utilized as a pair of read bit lines RB and /RBB areelectrically contacted with seventh and eighth metal electrical wirelayers 69 g and 69 h of second metal electrical wire group. Fifth metalelectrical wire layers 71 e of third metal electrical wire group forfunctioning as a power supply ground VSS is electrically contacted withfifth metal electrical wire layer 69 e of second metal electrical wiregroup. Configurations shown in FIG. 7 a to FIG. 7 c are an originalpatterned configuration in which all layers between first layer andsecond successive layer are overlapped. However, it is difficult todistinct from a boundary of various regions in case of the show of theoverlapped configuration within FIG. 7 a to FIG. 7 c. Therefore, theoverlapped configuration is not shown in FIG. 7 a to FIG. 7 c.

FIG. 8 a to FIG. 8 c are schematic layout diagrams for explainingprocess steps of second embodiment of a multi-port SRAM according to thepresent invention.

In second embodiment of a multi-port SRAM according to the presentinvention, long axes of the active regions for functioning as first andsecond load transistors TL1 and TL2 are a horizontal direction. Also,only a vertical direction is a direction at which first and second metalelectrical wire layers 85 a and 85 b pass on the active regions. Infirst embodiment of a multi-port SRAM according to the presentinvention, however, any portions of which the metal electrical wirelayers pass on the active regions are formed in a vertical direction anda perpendicular direction to a horizontal direction. Only a verticaldirection at which the metal electrical wire layers pass on the activeregions is embodied in second embodiment of a multi-port SRAM accordingto the present invention.

As known in FIG. 8 a, an N-type well region 82 is formed within some ofa cell formation region 81 in order to define regions of a pair of firstand second load transistors TL1 and TL2. First and second active regions84 a and 84 b have their long axes which are parallel with a horizontaldirection in the cell formation region 81 and are separated from eachsecond at an opposition. On the central portion of P-type well regionwhich is second region except the N type well region 82 within the cellformation region 81 are third active region 84 c which has its long axisin a horizontal direction. Also, fourth active region 84 d is aseparation region between first and second active regions 84 a and 84 b.Fifth active region 84 e is formed to be extended from the central lowerportion of third active region 84 c to a vertical direction. At thelower portion of fifth active region 84 e, sixth and eighth activeregions 84 f and 84 h are respectively extended to its left side in ahorizontal direction and seventh and ninth active regions 84 g and 84 iare respectively extended to its right side in a horizontal direction.Tenth and twelfth active regions 84 j and 84 l and eleventh and thirteenactive regions 84 m and 84 k have a symmetrically face configuration atan opposition. These active regions 84 j and 84 l are respectivelyextended to their lower portions to be vertical against eighth activeregion 84 h. These active regions 84 m and 84 k are respectivelyextended to their lower portions to be vertical against seventh activeregion 84 g. As gate electrodes of first load transistor TL1, firstwrite drive transistor WTD1, and first read drive transistor RTD1 isutilized first metal electrode layer 85 a which includes a first part topass on the central of first active region 84 a in a horizontaldirection, a second part to be extended to the first part in ahorizontal direction, and a third part to be passed on perpendicularlyto the second part in a vertical direction. Second metal electrode layer85 b has a face configuration against first metal electrode layer 85 a.As gate electrodes of second load transistor TL2, second write drivetransistor WTD2, and second read drive transistor RTD2 is utilizedsecond metal electrode layer 85 b which passes on the central of secondactive region 84 b in a horizontal direction and cross-passes on thirdand sixth active regions 84 c and 84 f in a vertical direction. Thirdand fourth metal electrode layers 85 c and 85 d are utilized as gateelectrodes of first and second write access transistors WTA1 and WTA2which cross-passes third active access transistor 84 c through theirboth sides on basis of first and second metal electrode layers 85 a and85 b. Fifth and sixth metal electrode layers 85 e and 85 f are utilizedas gate electrodes of first and second access transistors RTA1 and RTA2and have a configuration in which tenth and eleventh active regions 84 jand 84 k are cross-passed in a horizontal direction.

First to third contact regions CT11, CT12, and CT13 for first commonnode CN1 are respectively formed on third active region 84 c of firstelectrodes of third metal electrode layer 85 c, the upper portion ofsecond metal electrode layer 85 b, first active region 84 a of secondelectrode of first metal electrode layer 85 a, and the contact region ofa power supply voltage VCC formed on first and second active regions 84a and 84 b and fourth active region 84 d of first and second metalelectrode layers 85 a and 85 b. First to third contact regions CT21,CT22, and CT23 for second common node CN2 are respectively formed onthird active region 84 c of first electrodes of fourth metal electrodelayers 85 d, the upper portion of first metal electrode layer 85 a, andsecond active region 84 b of second electrode of second metal electrodelayer 85 b. Contact regions of a pair of write bit lines WB and /WBB arerespectively formed on third active region 84 c of second electrodes ofthird and fourth metal electrode layers 85 c and 85 d. Contact regionsof a write word line WLL are respectively positioned at the edge of thecell formation region 61 and are respectively formed on the end portionof third and fourth metal electrode layers 85 c and 85 d. Contactregions of a power supply ground VSS are formed on fifth active region84 e. Contact regions of a read word line RWL are respectivelypositioned at the edge of the cell formation region 81 and arerespectively formed on the end portion of fifth and sixth metalelectrode layers 85 e and 85 f Contact regions of a pair of read bitlines RB and /RBB are respectively formed on twelfth and thirteen activeregions 84 l and 84 m of first electrodes of fifth and sixth metalelectrode layers 85 e and 85 f. Fourth active region 84 d is a regionfor mediating a well bias of the N-type well region.

Entire layout configuration of first metal electrical wire group issimilar like those shown in FAIG. 7 b, but metal electrical wire laidout configuration for being electrically provided with a power supplyvoltage VCC are very different. This difference appears on that themetal electrode layers of first and second load transistors TL1 andsecond formed on first and second active regions 84 a and 84 b are notpositioned at the same horizontal direction as fourth active region 84 dby the variation of a long axis of first and second active regions 84 aand 84 b. Therefore, the metal electrical wire laid out configurationhas a vertical part to be perpendicular to the edge of the cellformation region 81.

In FIG. 8 b, first metal electrical wire layer 87 a of first metalelectrical wire group is electrically contacted with contact regions ofa power supply voltage VCC of fourth active region 84 d and firstelectrodes of first and second load transistors TL1 and TL2. Second andthird metal electrical wire layers 87 b and 87 c of first metalelectrical wire group are respectively coupled to a contact region of awrite word line WWL. Fourth metal electrical wire layer 87 d of firstmetal electrical wire group is electrically connected to first to thirdcontact regions CT11, CT12, and CT13 for first common node CN1. Sixthand seventh metal electrical wire layers 87 f and 87 g of first metalelectrical wire group are electrically connected to contact regions of apair of write bit lines WB and /WBB. Eighth and ninth metal electricalwire layers 87 h and 87 j of first metal electrical wire group areelectrically connected to contact region of a read word line RWL. Tenthmetal electrical wire layer 87 j of first metal electrical wire group iselectrically connected to contact regions of a power supply ground VSSand is extended to the upper side of third active region 84 c. Eleventhand twelfth metal electrical wire layers 87 k and 87 l of first metalelectrical wire group are electrically connected to contact regions of apair of read bit lines RB and /RBB. A first plurality of via holes 88are formed on first to twelfth metal electrical wire layers 87 a to 87 lof first metal electrical wire group.

In FIG. 8 c, first metal electrical wire layer 89 a of second metalelectrical wire group is electrically contacted with first metalelectrical wire layer 87 a of first metal electrical wire group and isutilized as a power supply voltage VCC. Second metal electrical wirelayer 89 b of second metal electrical wire group is electricallycontacted with second and third metal electrical wire layers 87 b and 87c of first metal electrical wire group. Third to fifth metal electricalwire layer 89 c to 89 e of second metal electrical wire group areelectrically contacted with sixth, seventh, and tenth metal electricalwire layers 87 f, 87 g, and 87 j of first metal electrical wire group.Sixth metal electrical wire layer 89 f of second metal electrical wiregroup is electrically contacted with eighth and ninth metal electricalwire layers 87 h and 87 i of first metal electrical wire group forfunctioning as a read word line RWL. Seventh and eighth 89 g and 89 hare separated from each second and are electrically contacted witheleventh and twelfth metal electrical wire layers 87 h and 87 i of firstmetal electrical wire group. A second plurality of via holes 90 areformed on third, fourth, fifth, seventh, and eighth metal electricalwire layers 89 c, 89 d, 89 e, 89 g, and 89 h.

First and second metal electrical wire layers 91 a and 91 b of thirdmetal electrical wire group for being utilized as a pair of write bitlines WB and /WBB are electrically contacted with third and fourth metalelectrical wire layers 89 c and 89 d of second metal electrical wiregroup via the second plurality of via holes. Third and fourth metalelectrical wire layers 91 c and 91 d of third metal electrical wiregroup for being utilized as a pair of read bit lines RB and /RBB areelectrically contacted with seventh and eighth metal electrical wirelayers 89 g and 89 h of second metal electrical wire group. Fifth metalelectrical wire layers 91 e of third metal electrical wire group forfunctioning as a power supply ground VSS is electrically contacted withfifth metal electrical wire layer 89 e of second metal electrical wiregroup.

In embodiments of a multi-port SRAM according to the present invention,a number of contact regions to be positioned at the same horizontaldirection are limited to for example 6, rather than 4 or 5. Moreover, itis to obtain a necessary margin of a layout configuration on a cellarray by the above limitation, or by making contact regions of a powersupply ground VSS to be positioned at the lower of drive transistorwithin a cell formation region. Further, contact regions of a powersupply voltage VCC and a power supply ground VSS included in first unitcell and in second unit cell neighbored to the corresponding first unitcell are independently formed by a unit cell of a cell array, therebybeing happened only at in-operation of first unit cell, regardless ofsecond unit cell neighbored to the corresponding first unit cell in caseof the electrical disconnection of contact regions of the power supplysource VCC and VSS to metal electrode layers within the correspondingfirst unit cell.

According to a multi-port SRAM of the present invention, obtainment of anecessary margin of a layout configuration on a cell array is to be ableto reduce an occupation area of a memory cell on a substrate. A width ofoccupation region of load transistors is extended to a verticaldirection, resulting in degrading its trust and decreasing its operationspeed.

1. A multi-port static random access memory wherein a two-port staticrandom access memory comprises a first plurality of active regions whichare separated from each other within a cell formation region, a firstplurality of metal electrode layers which are respectively passed on thefirst plurality of said active regions, and a power supply source whichis electrically contacted with the first plurality of said metalelectrode layers, wherein said metal electrode layers included in firstunit cell and in second unit cell neighbored to the corresponding firstunit cell of the first plurality of said metal electrode layers arecommonly connected to said power supply source, comprising: a secondplurality of active regions formed within the cell formation region; anda second plurality of metal electrode layers to be passed on the secondplurality of said active regions and to be independently and separatelyconnected to said power supply source, wherein the independence andseparation of the connection to said power supply source is between saidmetal electrode layers included in first unit cell in the secondplurality of said metal electrode layers and said metal electrode layersincluded in the second unit cell neighbored to the corresponding firstunit cell in the second plurality of said metal electrode layers.
 2. Amulti-port static random access memory according to claim 1 wherein longaxes of some of said active regions in the second plurality of saidactive regions are respectively extended to a vertical direction.
 3. Amulti-port static random access memory according to claim 1 wherein theseconds of said active regions in the second plurality of said activeregions are integrated with each other.
 4. A multi-port static randomaccess memory according to claim 3 wherein long axes of the integratedactive regions in the second plurality of said active regions arerespectively extended to a horizontal direction.
 5. A multi-port staticrandom access memory according to claim 1 wherein the upper portion ofthe second plurality of said active regions are respectively andcommonly contacted with a write word line only in first unit cell,regardless of second unit cell neighbored to the corresponding firstunit cell.
 6. A multi-port static random access memory according toclaim 1 wherein the lower portion of the second plurality of said activeregions are respectively and commonly contacted with a read word lineonly in the first unit cell, regardless of second unit cell neighboredto the corresponding first unit cell.
 7. A multi-port static randomaccess memory according to any first of the preceding claims wherein anumber of contact regions on the second plurality of said active regionsare smaller than those of contact regions on the first plurality of saidactive regions, in a horizontal direction.
 8. A multi-port static randomaccess memory comprising a plurality of unit cells each including: afirst pair of first and second load transistors having their gateelectrodes respectively formed by first and second metal electrodelayers on first and second active regions, their first electrodes forbeing electrically contacted with a power supply voltage, and theirsecond electrodes for being electrically connected to a first pair offirst and second common nodes only in first unit cell, regardless ofsecond unit cell neighbored to the corresponding first unit cell; afirst pair of first and second write drive transistors having their gateelectrodes and first electrodes for being electrically and respectivelyconnected to the corresponding one of the first pair of said first andsecond common nodes; a first pair of first and second read drivetransistors having their first electrodes for being electrically andrespectively connected to the corresponding one of a second pair ofthird and fourth common nodes, and their gate electrodes for beingelectrically and respectively connected to the corresponding first ofthe first pair of said first and second common nodes; a first pair offirst and second write access transistors having their first electrodesfor being electrically and respectively connected to the correspondingone of the first pair of said common nodes, their gate electrodes forbeing electrically and respectively connected to the corresponding oneof the second electrodes of the pair of said first and second loadtransistors, and their second electrodes for being electrically andrespectively connected to the corresponding first of a pair of write bitlines; and a first pair of first and second read access transistorshaving their gate electrodes for being electrically and respectivelyconnected to the corresponding one of a pair of read word lines, theirfirst electrodes for being electrically and respectively connected tothe corresponding one of the pair of first and second read drivetransistors, and their second electrodes for being electrically andrespectively connected to the corresponding one of a pair of read bitlines.
 9. A multi-port static random access memory according to claim 8,wherein the second electrodes of the first pair of said first and secondwrite access transistors included in first unit cell of the plurality ofsaid unit cells are electrically coupled to the corresponding electrodesof a second pair of write access transistors included in second unitcell neighbored to the corresponding first unit cell of the plurality ofsaid unit cells, and the second electrodes of the first pair of saidfirst and second read access transistors included in first unit cell ofthe plurality of said unit cells are electrically coupled to thecorresponding electrodes of a second pair of read access transistorsincluded in second unit cell neighbored to the corresponding first unitcell of the plurality of said unit cells.
 10. A multi-port static randomaccess memory according to claim 8, wherein each of said unit cellsfurther includes a plurality of active regions formed within the cellformation region, and a plurality of metal electrode layers to be passedon said active regions and to be independently and separately connectedto said power supply source.
 11. A multi-port static random accessmemory according to claim 10, wherein the plurality of said activeregions includes first, second, and fourth active regions for beingindependently separated from each second and second regions for beingdependently integrated from each other.
 12. A multi-port static randomaccess memory according to claim 10, wherein the plurality of metalelectrode layers include: a first metal electrode layer having aconfiguration in which its two portions are perpendicular to each secondand at least first portion of said first, third, and sixth activeregions are passed on, a second metal electrode layer for being formedso that it may have a symmetrically mutual face configuration with saidfirst metal electrode layer and so that at least first portion of saidsecond, third, seventh active regions may be passed on, a third metalelectrode layer for being formed so that any portion of said thirdactive region is passed on, a fourth metal electrode layer for beingformed so that any portion of said third active region may be passed on,a fifth metal electrode layer for being formed so that any portion ofsaid tenth active region may be passed on, and a sixth metal electrodelayer for being formed so that it may have a symmetrically mutual faceconfiguration with said fifth metal electrode layer.
 13. A multi-portstatic random access memory according to claim 10, claim 11, or claim 12wherein a contact region of said power supply voltage is respectivelyformed on said first, second, and fourth active regions and on firstelectrodes of first and second metal electrode layers, and first tothird contact regions for said first common node are respectively formedon said third active region of first electrode of said third metalelectrode layer, on the upper portion of said second metal electrodelayer, and on first active region of second electrode of first metalelectrode layer.
 14. A multi-port static random access memory accordingto claim 10, claim 11, or claim 12 wherein first to third contactregions for said second common node are respectively formed on saidthird active region of first electrode of said fourth metal electrodelayer, the upper portion of first metal electrode layer, and secondactive region of second electrode of said second metal electrode layer.15. A multi-port static random access memory according to claim 10,claim 11, or claim 12 wherein contact regions of the pair of said writebit lines and are respectively formed on said third active region ofsecond electrodes of said third and fourth metal electrode layers.
 16. Amulti-port static random access memory according to claim 10, claim 11,or claim 12 wherein contact regions of said write word line arerespectively positioned at the edge of the cell formation region and arerespectively formed on the end portion of said third and fourth metalelectrode layers, and contact regions of said power supply ground areformed on said fifth active region.
 17. A multi-port static randomaccess memory according to claim 10, claim 11, or claim 12 whereincontact regions of said read word lines are respectively positioned atthe edge of the cell formation region and are respectively formed on theend portion of said fifth and sixth metal electrode layers, and contactregions of the pair of said read bit lines are respectively formed onsaid twelfth and thirteen active regions of first electrodes of saidfifth and sixth metal electrode layers.
 18. A multi-port static randomaccess memory according to claim 10 wherein said unit cells furtherincludes a plurality of metal electrical wire groups having: a firstmetal electrical wire group consisting of first metal electrical wirelayer for being electrically contacted with the contact regions of saidpower supply voltage and with first electrodes of first and second loadtransistors, second and third metal electrical wire layers for beingrespectively coupled to the corresponding contact region of said writeword lines, fourth metal electrical wire layer for being electricallyconnected to said first to third contact regions for said first commonnode, sixth and seventh metal electrical wire layers for beingelectrically connected to the contact regions of the pair of write bitlines, eighth and ninth metal electrical wire layers for beingelectrically connected to the corresponding contact region of said readword lines, tenth metal electrical wire layer for being electricallyconnected to the contact regions of said power supply ground and forbeing extended to the upper side of said third active region, andeleventh and twelfth metal electrical wire layers for being electricallyconnected to the contact regions of the pair of said read bit lines. 19.A multi-port static random access memory according to claim 18 whereinthe plurality of metal electrical wire groups further have a secondmetal electrical wire group consisting of a first metal electrical wirelayer for being electrically contacted with said first metal electricalwire layer of said first metal electrical wire group and for beingutilized as said power supply voltage, a second metal electrical wirelayer for being electrically contacted with said second and third metalelectrical wire layers of said first metal electrical wire group, thirdto fifth metal electrical wire layers for being electrically contactedwith said sixth, seventh, and tenth metal electrical wire layers of saidfirst metal electrical wire group, a sixth metal electrical wire layerfor being electrically contacted with said eighth and ninth metalelectrical wire layers of said first metal electrical wire group and forfunctioning as the corresponding first of said read word lines, andseventh and eighth metal electrical wire layers for being separated fromeach second and for being electrically contacted with said eleventh andtwelfth metal electrical wire layers of said first metal electrical wiregroup.
 20. A multi-port static random access memory according to claim18 wherein the plurality of metal electrical wire groups further have athird metal electrical wire group consisting of first and second metalelectrical wire layers for being utilized as the pair of said write bitlines and for being electrically contacted with said third and fourthmetal electrical wire layers of said second metal electrical wire groupvia a second plurality of via holes, third and fourth metal electricalwire layers for being utilized as the pair of said read bit lines andfor being electrically contacted with said seventh and eighth metalelectrical wire layers of said second metal electrical wire group, fifthmetal electrical wire layers for functioning as said power supply groundand for being electrically contacted with said fifth metal electricalwire layer of said second metal electrical wire group.
 21. A multi-portstatic random access memory according to claim 11 wherein long axes ofsaid first and second active regions each is in a horizontal direction.22. A multi-port static random access memory according to claim 12wherein said first metal electrode layer includes a first part to passon the central of said first active region in a horizontal direction, asecond part to be extended to said first part in a horizontal direction,and a third part to be passed on perpendicularly to said second part ina vertical direction and to successively cross-pass said third and sixthactive regions.
 23. A multi-port static random access memory accordingto claim 12 wherein said second metal electrode layer has a symmetricalface configuration at which the central of said first active region ispassed on in a vertical direction and said third and sixth activeregions are successively cross-passed.
 24. A multi-port static randomaccess memory according to claim 18 wherein electrodes of said firstmetal electrical wire layer of said first metal electrical wire group isnot positioned at the same horizontal direction as said fourth activeregion, thereby having a vertical part to perpendicular to the edge ofthe cell formation region.